A memory block of a memory device, such as is used in NAND or NOR memory, may comprise a group of strings of memory cells that share the same set of access lines. The memory block may be grouped into a one or more pages (also referred to as “tiles”), and each page may comprise memory cells corresponding to at least a portion of a respective tier of each of the group of strings.
FIG. 1 is a simplified schematic diagram of a conventional architecture for a portion of a memory device including a tile group 100 including a first tile 105A and a second tile 105B. In this conventional architecture, the first tile 105A and the second tile 105B are offset from each other in the Y direction with vertical string driver circuitry 125 therebetween. A portion of the tile group 100 shown in FIG. 1 is part of the CMOS under array (CUA) space located under a memory array. Thus, the tile groups 105A, 105B are coupled to a memory array, which is not shown so as not to obscure the figure.
Each tile 105A, 105B includes block select circuitry 120 coupled to the vertical string driver circuitry 125 through block select lines 122, which in turn couple to access lines (e.g., word lines) coupled to the memory array. The block select lines 122 coupling the block select circuitry 120 and the vertical string driver circuitry 125 are shown as a single line for simplicity, however, it should be understood that the block select lines 122 include multiple lines but that a single line is shown for simplicity. Each tile 105A, 105B may further include available space for additional circuitry 130 such as periphery circuitry and/or other supporting circuitry (e.g., charge pumps, controllers, etc.) for the memory array that may be beneficial to include within the CUA space. In the conventional architecture layout, approximately half (50%) of the space is occupied by the page buffer 110, in part, because of the configuration of the block select circuitry 120. As a result, the flexibility in the configuration of the page buffer 110 may be limited. The block select circuitry 120 serves the tile group 100 and is split between the first tile 105A and the second tile 105B but on opposite ends of the vertical string driver circuitry 125 in order to couple to different portions thereof.
FIG. 2 is a simplified schematic diagram of a conventional architecture for a tile group 200 including multiple planes 108A, 108B having multiple tile groups (e.g., 105A & 105B). In particular, the first plane 108A includes tiles 105A-105H and the second plane 108B includes tiles 1051-105P. In this conventional architecture, the tile group shown in FIG. 1 is replicated to form the planes 108A, 108B. As with FIG. 1, each tile group includes block select circuitry 120 split between the two tiles of the tile group. As a result, each tile 105A-105P may have a page buffer 110 that occupies approximately 50% of the tile space, and the placement of any additional circuitry 130 may be fixed to be the remaining area on the other half of the tile that is not being occupied by the block select circuitry 120.
FIG. 3 is a simplified schematic diagram 300 of a conventional architecture for a tile group including multiple planes 108A, 108B having multiple tile groups (e.g., tiles 105A, 105B). The layout of page buffers 110 may be similar to that of FIG. 2; however, the block select circuitry 120 that is part of the first tile group (e.g., tiles 105A, 105B) may include block select lines 122 that extend to the other vertical string driver circuitry 125 of its respective plane 108A, 108B. For example, the portion of the block select circuitry 120 located within the first tile 105A may be coupled to the vertical string drivers associated with tile pairs 105C/105D, 105E, 105F, etc. As a result, the block select circuitry 120 may provide global support for each tile in its plane. While doing so may free up space for additional circuitry 130 by reducing the block select circuitry 120, the page buffer 110 may still occupy approximately 50% of the available tile space as a result of the configuration of the global block select circuitry 120.